Jira
Vinita Singh
Senior Verification Engineer
Cork
Summary
Experienced ASIC Design Verification Engineer with 7 years of experience in semiconductor industry. Worked on various CPUs and IP level protocol. Excellent reputation for resolving problems and debugging skills.
*Visa status: STAMP #4, ready to join immediately*
Overview
7
7
years of professional experience
2
2
years of post-secondary education
Work History
Sr. Silicon Design Engineer(Verification)
AMD
09.2022 - Current
- Worked on Back End level verification of Data Accelerator(DACC) at IP level.
- Worked in Weisshorn Back End team-Completed clk uvc testbench development and basic work level experience in Scalable Data Port.
- Owned one of the feature in Mi450 BE Accelerator - DMA enable, for that worked on testbench development , reading specs, developed test plans- executed them by writing tests, functional coverage after discussion with RTL designers.
- Debugging and finding out critical RTL bugs. Worked with designers to fix them.
- Implemented coverage-driven verification techniques for improved test effectiveness . Completed code coverage for one of the design block- line, toggle and FSM coverage.
- Skills used in above- System Verilog, UVM, Verdi.
- Implemented coverage-driven verification techniques for improved test effectiveness .
- Utilized advanced debug tools to effectively isolate issues within the hardware-software interface quickly and accurately.
- Established strong working relationships with design engineers for efficient knowledge transfer and collaboration throughout the verification process.
CPU Verification Engineer
ARM Embedded Pvt Ltd
03.2018 - 03.2022
- Worked on Top level verification for Neoverse (Cortex-A76/A78,Cortex-X1) ARM's server class CPU as part of cross site team.
- Worked on Top level verification of TC22 Little class (Cortex -A) CPU
- Independently owned RIS tool on above CPUs verification.
- Gained working knowledge of ARMv8+ M&A Class CPU Architecture and AMBA bus protocols
- Good knowledge in CPU Architecture and ARM V8 ,V8.x and V9 Architecture.
- Proficient in Server class CPU Micro-architecture
- Mentored juniors in ARM from last 2 years.
- Worked on verification infrastructure based on Perl
- Experience with debugging RTL code on Verdi platform
- Worked on Test planning, Coverage development and closure, Stimulus development, System Verilog based checkers.
- Developed stimulus for core level Microarchitectural Test plan scenarios and Architectural scenarios, and designer requirements for bug hunting.
- Handled Test bench and Infra work for team for 6 months.
- Handled independently RAS feature for crucial milestones beta,LAC, EAC and REL achieved 100% pass rate.
Research Assistant
CORI Lab, PES University
07.2017 - 02.2018
- FPGA implementation on Digital Signal Processing and Communication system Algorithm development , Digital system design.
- Implementation of Independent Component Analysis on FPGA
- Designing and Implementing Modulators Using Vivado HLS
- Design and Evaluation of SoC based Modulators
- IP/SoC worked on creating Zynq processor and integrating IP's to it, and processing algorithm on SoC, and interfacing different peripheral like UART, gpio, led, dip switch, push button.
- Planned, modified and executed research techniques, procedures and tests.
Education
Master of Technology - Electronics And Communications Engineering
PES University
Bangalore, India 08.2015 - 08.2017
Bachelor of Technology - Electronics And Communications Engineering
Rajasthan Technical University
Kota, India 08.2007 - 2012.03
Skills
ASIC Design
RTL Verification
CPU Architecture
CPU microarchitecture
Debugging
Accomplishments
- Awarded with the BRAVO Award for valuable contribution in identifying critical bugs in RTL in ARM.
- Achieved 100% RTL pass rate by completing RAS work with accuracy and efficiency that results in finding 4 functional bugs.
Software
Mentor Graphics – QuestaSim
Synopsys – Verdi
Verilog HDL
Perl scripting
UVM
System verliog
C/C
Windows & Linux
Projects
ARM Cortex-X1 and Cortex-A78 CPU Core verification(Big Cores-Server class, mobile, laptops and automotive processors)
- Done Top-level CPU Verification.
- Helped in stabilizing RTL from 50% pass rate to around 99%.
- In this process filled around 250 RTL , CPU Model and tool Bugs.
- Written function coverage for some critical features.
- Collected toggle and opcode coverage.
- Worked on RAS activity by having ECC in EAC and REL milestones.
- Independently handled RIS tool in all the maintainence releases.
ARM Cortex-A76 CPU Verification
- Independently worked on its maintainence release using RIS tool.
- Backported RAS checker according to Cache organization of all the RAMs.
- Found 3 critical functional bugs after REL phase.
ARM TC22 cores Cortex-550(Little core)
- Done Top-level CPU Verification using RIS tool.
- Owned testbench for 4 months. Worked on bringing up smoke CI by using new tool.
- Owned RAS feature- worked on cache organization for all the RAMs from the scratch in checker.
- Changed the infrastructure of RAS feature according to new centralized RAM model.
- Found some RTL bugs and improved checker also.
- Worked on designer concerns also based on RAS.
Publication
FPGA implementation of blind source separation using a novel ICA algorithm
IEEE International Conference on Consumer Electronics-Asia (ICCE-Asia), 2017 · Mar 8, 2018
Design and Evaluation of a System on Chip based Modulator
2019 International Conference on Wireless Communications Signal Processing and Networking (WiSPNET)
Timeline
Sr. Silicon Design Engineer(Verification)
AMD
09.2022 - Current
CPU Verification Engineer
ARM Embedded Pvt Ltd
03.2018 - 03.2022
Research Assistant
CORI Lab, PES University
07.2017 - 02.2018
Master of Technology - Electronics And Communications Engineering
PES University
08.2015 - 08.2017
Bachelor of Technology - Electronics And Communications Engineering
Rajasthan Technical University
08.2007 - 2012.03
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