Tarun Malviya

Work History

Analog Devices International

Limerick

02.2023 - Current

Leading Deposition process team of Backend Workcentre
Time-bound process qualification and production release of the new Novellus C2 Sequel and Endura systems for production
Working with Vendors for defining scope of Process Support on new Dep toolsets
Supported porting of different processes (Dielectric Deposition) from sister fabs in the US by developing unit-steps/capabilities on alternate toolsets where matching tool not available
Also, provided remote support to sister fabs in establishing the FSG process on Applied HDP Ultima chambers
Proposed and executed an action plan for defect reduction on existing Novellus C2 platforms through recipe optimization & achieved a 30% reduction in particle performance control limits
Defining and executing CIP for the deposition team.

Thin Film Module, Semiconductor Laboratory (ISRO)

Mohali

07.2022 - 01.2023

Successfully managed a team of three process engineers and five techs, providing effective leadership and guidance
Planned and projected equipment replacement by defining requirements to senior management for module upgradation and capacity enhancement
Conducted new material qualification as part of vendor development initiatives, ensuring a robust and reliable supply chain
Took the lead in driving Continuous Improvement Projects (CIP) for the module, implementing effective process enhancements and achieving operational efficiency.

Semiconductor Laboratory (ISRO)

Mohali

12.2017 - 06.2022

Experience in Unit step development, optimizations, troubleshooting of various PECVD process on Novellus Concept II Sequel, ULVAC & Applied Materials platform (Centura,Endura) for HDP USG, FSG, DxZ (TEOS & Silane), WxZ, SIP Ti, TTN & IMP Ti chambers
Also, hands on experience on metrology tools like FTIR, Ellipsometer, Stress, XRF, 4 point probe
Defect reduction through implementation of best practices and optimisation of operating procedures
Introduced new surface preparation step to eliminate any flaking of barrier metal from edges/bevel and thus reducing killer defect
Implementing new seasoning practice to reduce MOCVD TiN defects by 20%
Continuous process improvement activities like-Improved Cs resistance from baseline process by optimization of Cs/Via liner/barrier recipe and W deposition recipe, HDP void free gap fill etc
Developed & released for production an Antifuse element for OTP memory to be integrated for in-production BEOL flow.

Semiconductor Laboratory (ISRO)

Mohali

04.2014 - 12.2017

Experience in development, qualification & modification of Wet Cleaning/ Etching/Stripping Unit steps on LAM Spin Processor SEZ (SP223), SES Japan Wet Benches, Semitool Spray Spectrum Tool (SST), Brooks Sorter & KLA Tencor Surfscan (SP1) form/130nm CMOS process
Recipe creation, Optimization & process troubleshooting
Prepared technical specification for procuring FEOL Clean Wet Bench & wafer front, back & bevel clean scrubber for 180nm technology node
Major scrap reduction due to wafer backside contamination by 1st releasing a containment plan and then qualifying alternate chemical for cleaning capacitor etch clean
Qualification of raw material introduced from new vendors in Line.

Vikram Sarabhai Space Centre, ISRO

Thiruvananthapuram

09.2007 - 03.2014

Responsible for Electrical Integration of various Avionic subsystems, sensors, actuators & feedback systems of solid propellant stages
Carried out sub-system integration, integrated checks and post flight data analysis (PFA) for 11 PSLV & 4 GSLV Launch Vehicles booster stage including India's 1st Moon & Mars Mission.
Instrumental in design and development of electrical system integration scheme for ISRO's
RLV-TD booster stage and GSLV-Mk3 strap-on stages