Shradha Narayana Gowda
Dublin
Summary
Highly skilled Pre-Silicon Validation Engineer with 3+ years of experience in IP validation at Intel. Proficient in Universal Verification Methodology (UVM) for building reusable and scalable testbenches. Extensive experience with debugging and developing testbenches using Eclipse DVT, Verdi, and industry-standard verification tools. Skilled in working within Linux environments and using Git for version control. Strong expertise in functional verification, and achieving high verification coverage. Effective collaborator with cross-functional teams to ensure high-quality silicon designs
Overview
8
8
years of professional experience
1
1
Certification
Work History
Design Validation Engineer
Intel
11.2021 - Current
- IP Verification: Validated IPs using UVM-based methodology, focusing on testbench development, simulation, and ensuring comprehensive functional and code coverage.
- Testbench Development: Created modular, reusable UVM testbenches for IP functional validation. Automated various test scenarios and enhanced coverage with constraint-driven verification.
- Debugging and Code Development: Created modular, reusable UVM testbenches for IP functional validation. Automated various test scenarios and enhanced coverage with constraint-driven verification.
- Git Version Control: Managed testbench and verification environment using Git for version control. Effectively collaborated with teams to track code changes, manage branches, and ensure synchronization of design files.
- Linux Environment: Worked extensively in Linux-based environments for simulation, scripting, and automation.
- Verification Plan: Created detailed verification plans and drove verification closure strategies to achieve required functional and coverage metrics. Ensured test scenarios aligned with design specifications.
- Simulation & Debugging: Used NBFlow, and Verdi for RTL simulation and debugging. Analyzed complex waveforms and improved test coverage using constrained random verification techniques.
- Collaboration: Worked closely with RTL design teams, and system architects to define verification strategies and align design requirements.
- Functional Coverage: Monitored functional and code coverage, ensuring adherence to project-specific coverage metrics. Worked on constraint random testing techniques to improve test efficiency.
- Documentation & Reporting: Generated detailed validation reports, summarized verification results, and proposed optimizations to improve overall IP validation efficiency.
Sr Process Executive
Infosys Ltd
03.2019 - 06.2020
- Senior process executive in detecting the fraud cases of the credit card
- Enhanced customer satisfaction ratings by resolving issues efficiently
- Interacted with customers with the utmost professionalism to solve various problems
- Optimized processes by collaborating with upper management to implement innovative technologies
- Assisted customers with product usage and troubleshooting issues
- Actively participated in encouraging the team by conducting team building activities
- Awarded employee of the month thrice.
Assistance System Engineer
Tata Consultancy Limited
10.2016 - 10.2017
- Trained on ASP.net, Java, JavaScript, LINUX, SQL Server
- Developed and customized an IBM developed tool called MAXIMO
- Backend development of the tool, Created server architecture and maintained it
- Managed system-wide operating system and software deployments, as well as any related upgrade problems
- Answered and triaged requests for assistance in order to provide top-notch support
- Trained team members and users in newly implemented and emerging technology to enhance business productivity.
Education
Master of Science - Electronics And Communications Engineering
Technological University of Dublin
Dublin, Ireland10-2021
Bachelor of Science - Telecommunications
Siddaganga Institute of Technology
Tumkur, India08-2016
Skills
- Verification Methodologies: Universal Verification Methodology (UVM), SystemVerilog
- Languages: SystemVerilog, Verilog, C/C, VHDL, Embedded C
- Verification Tools: Verdi, Eclipse DVT
- Debugging Tools: Verdi, DVE
- Version Control: Git, Git Hub
- Development Tools: XILINX IDE, MATLAB
Technical Skills
- Operating Systems: Linux, Windows
- Microsoft office: Microsoft Word, Microsoft Excel, Microsoft PowerPoint, Outlook
- Strong problem-solving abilities
- Excellent communication and collaboration skills
- Attention to detail
- Time management and task prioritization in a fast-paced environment
Soft Skills
Languages
Kannada
English
Hindi
Telugu
Hobbies and Interests
- Travelling
- Sketching
- Cycling
- Swimming
Personal Information
- Date of Birth: 03/01/1995
- Gender: Female
Certification
- UVM Methodology Couse – Cliff Cummings of Sunburst Design, 2022
- SystemVerilog for Verification Course– Hardent Training Institution, 2022
- Advanced UVM Verification Course - Cliff Cummings of Sunburst Design, 2024
- Intel Internal Training: Pre-Silicon Validation and UVM Best Practices
Timeline
Design Validation Engineer
Intel
11.2021 - Current
Sr Process Executive
Infosys Ltd
03.2019 - 06.2020
Assistance System Engineer
Tata Consultancy Limited
10.2016 - 10.2017
Master of Science - Electronics And Communications Engineering
Technological University of Dublin
Bachelor of Science - Telecommunications
Siddaganga Institute of Technology
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