Sahith
Ravur
Summary
Dynamic Associate Software Engineer with a proven track record at RTL Design, specializing in VLSI RTL development using VHDL/Verilog. Excelled in optimizing digital circuits for enhanced performance, achieving significant code efficiency improvements. Skilled in Java and collaborative problem-solving, consistently delivered high-quality design solutions, documented meticulously for team use.
Overview
1
1
year of professional experience
Work History
Associate Software Engineer
RTL Design
06.2024 - Current
VLSI RTL Developer
- Developed and validated RTL code for complex digital circuits using VHDL/Verilog.
- Collaborated with the design team to ensure high-quality design implementation.
- Conducted simulations and debugging to identify and fix issues in the design.
- Optimized the code for area, power, and performance.
- Participated in design reviews and provided feedback to improve the overall design process.
- Created comprehensive documentation for the design and implementation of the circuits.
Education
B.E - Electronics And Communications Engineering
Hindusthan College of Engineering And Technology
Coimbatore05-2023
Skills
- Java
- Verilog
- SQL
- HTML
- CSS
Hobbies
Playing and Watching Cricket
Listening Music
Languages
English
Full Professional
Telugu
Native or Bilingual
Timeline
Associate Software Engineer
RTL Design
06.2024 - Current
B.E - Electronics And Communications Engineering
Hindusthan College of Engineering And Technology
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