Radhika Unni
Meath
Summary
Formal Verification Engineer with a robust background at Intel, adept in enhancing network controller features and excelling in formal verification techniques. Specializes in SystemVerilog Assertions, showcasing leadership in Agile methodologies and debugging skills . Demonstrates expertise in scripting languages and a collaborative spirit, ensuring project milestones are surpassed with precision.
Overview
9
9
years of professional experience
Work History
Formal Verification Engineer
Intel
08.2021 - Current
- Currently working on the INTEL IPU Mount Morgan network controller, succeeding, and enhancing the features on the existing Mount Evans.
- Experiance in formal verification property checks on multiple IPs, most of the work around security IP. Property checks (Design verification) are done using System Verilog Assertions (SVA).
- Experience using various Formal Verification Technics such as Sequential Equivalence Checking, Coverage Analysis, Fault Injection etc.
- Closely working with SOC , IP designers and Architecture teams to help improve efficiency and productivity. Experience in LINUX based operating system.
- Created regression tests to assess the impact of changes made to existing systems.
- Worked with Agile and Scrum methodologies to accomplish project milestones and meet demanding timelines.
- Verification Test plan creation using Cadence VManager allowing analysis and coverage checks through vplan.
- Tools used: Cadence Jasper Gold - EDA Formal Verification platform. Also has some exposure to Synopsys VCformal mostly for investigative studies. DVT eclipe IDE - Used for verification code writing. VManager - Cadence Tool used mainly for test plan creation and running regressions. Verdi - Used mainly for assertion debugging (waveform debugging). GIT Version control. Various other continuous integration tools developed by INTEL for RTL code management, Process flow management.
Test Engineer
Valeo Vision Systems
Galway
10.2018 - 07.2021
- Driving Test Engineering best practices including software and Hardware standardisation from Prototyping through to Series Production
- Test Lead/process lead for Multiple test stations (Front end and Back End) which includes planning, resourcing and technical reviews for every processes
- Capitalize and share the know-how of industrial process needed in Testing strategies
- Follow up the implementation, qualification and start-up of stations
- Reading/reviewing Solidworks e-drawings for best fixture development for every process
- Works closely with project Teams in delivering new projects to production with clear focus on Cycle time targets, first time yield, Direct Labour and Test system Efficiency and utilisation
- Perform validation, capabilities, test coverage and stability performance of testers
- Quality defect, TLR analysis, FMEA, OQ/IQ/PQ studies
- Integration of testing equipments into manufacturing cells
- Perform FTA and PDCA analysis to ensure process reliability and stability
- Documentation activities - STI test specification, Checklists , Test coverage reports etc
- URS, DFM and DFT Checklist Review and Test coverage report Author
- Participate in RAISE and Standardization Committees to Ensure Products are adapted to testing process needs
Intern
ON Semiconductor
Cork
05.2018 - 09.2018
- Research Internship on Photon Detection Efficiency
- Analysis and characterisation of SensL SiPMs
- Worked on basic Design Principles of MPPC's
- Research thesis on photon detection efficiency and excess charge factor
Software Engineer
KPIT Technology Ltd.
09.2015 - 09.2017
- Testing Software for automotive vehicle IPC panel
- Developed Test Cases for validation of CAN stack
- Diagnostic Testing by analysing the diagnostic request and response messages using Diagnostic Engineering Tool
- Testing the software using dSPACE and Cognex Insight Explorer
- Analyse customer requirements and internal specification to be applied in testing strategies of products
- Performing verification and validation of requirement discrepancies or software defects
- Debugging of Software
- Performed multiple code reviews and technical lead support
Education
Master of Engineering Science - Electronics and Computer Engineering
University College Dublin
Dublin09.2018
Bachelor of Engineering - Electronics and Instrumentation Engineering
SRM University
Chennai08.2015
Skills
- Scripting languages proficiency: SystemVerilog, C, Python, LABVIEW
- Assertion-based verification
- Coding Platforms: codeblocks, visual studio, DVT eclipse
- Formal verification techniques: Sequential Equivalence checking, fault injection, formal coverage
- Formal Verification Platforms: Cadence Jasper Gold (SVA property checks and debugging)
- Code coverage analysis and Pre-Silicon Verification and Validation
- Knowledge on communication protocols such as CAN, LIN and FLEXRAY
- Instrument Panel Testing and Diagnostic testing
- Testing Tools: Test stand, DSPACE, Insight Explorer
Affiliations
- Ergonomic Assessor at Intel: Facilitated proper work setups for employees, ensuring a safe workplace and enhancing productivity.
- Women in Technology Committee Member, Intel Ltd: Supporting initiatives to encourage women in Intel and educational institutions to pursue engineering careers
- Mini Scientist Events at Intel: Initiative to engage young children in science activities and projects, fostering their interest in STEM.
- Corporate Social Responsibility (CSR) Initiatives at KPIT Ltd: Actively participated in and led various sustainability events, promoting environmentally responsible practices within the industry
Timeline
Formal Verification Engineer
Intel
08.2021 - Current
Test Engineer
Valeo Vision Systems
10.2018 - 07.2021
Intern
ON Semiconductor
05.2018 - 09.2018
Software Engineer
KPIT Technology Ltd.
09.2015 - 09.2017
Master of Engineering Science - Electronics and Computer Engineering
University College Dublin
Bachelor of Engineering - Electronics and Instrumentation Engineering
SRM University
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