LUZ VICTORIA CONTRERAS ZAPATA
Sixmilebridge,Co. Clare
Summary
Experienced Logic Design Engineer with 5 years in the field, applying various strategies, tools, and methods to ensure project goals were met, as well as design integrity. Experienced with Formal Verification tools, and developing scripts to automate and optimise tasks.
Overview
7
7
years of professional experience
4
4
years of post-secondary education
1
1
Certification
Work history
Logic IP Design Engineer
Intel R&D
Shannon, Co. Clare
08.2020 - 09.2025
- Worked as part of Inline Crypto Engine Design team, focusing on logic design, RTL coding, and simulation.
- Applied various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
- Executed verification tasks using Cadence Jasper (FPV and Conn) and Synopsys tools for test implementation on SoC, result analysis, and reviews.
- Improved efficiency and productivity by acquiring new skills and knowledge on different methodologies such as UVM
- Analysed simulation failures to identify the underlying causes of bugs to develop and implement effective resolutions.
- Provided detailed weekly reports and meetings to discuss coverage results and progress
- Designed scripts to optimise testing and validation:
- Auto-Generated Coverage script: To continuously generate and update coverage and assertions for key signals.
- Feedthrough Connection script: Would help identify connections that needed to be rewired due to feedthrough insertion between partitions
Silicon Development DFX Intern
Intel R&D
Shannon, Co. Clare
03.2019 - 08.2019
- Delivered multiple scripts for DFx Indicators, such as Test ID status reporting and verification, and SpyGlass validation.
- Optimised scripts for customised per-IP use due to demand from other teams
- Provided valuable support for successful company events and meetings.
- Temporarily took over SpyGlass DFT Analysis and Debugging tasks.
Education
BACHELOR OF ENGINEERING-BE - ELECTRONIC ENGINEERING
Limerick Institute of Technology
Limerick City, Co. Limerick, Ireland 09.2016 - 05.2020
Skills
- RTL Design
- Logic Design
- Design For Debug (DFD)
- Formal Verification
- SystemVerilog
- Verilog
- Tcl
- Python
- UVM Methodologies
- SoC debug
- Cadence Jasper tools
- Spyglass - Lint & CDC
- Problem Solving
- Artificial Intelligence Fundamentals
- Resourcefulness
- Adapting to new technologies
- Resilience under pressure
- Microsoft Office Suite
Certification
IBM Certifications: Jul 2024
- Artificial Intelligence Fundamentals
- Natural Language Processing
- Supervised Learning Methods
- Unsupervised Learning Methods
- Data Analytics for Machine Learning
Cadence Certifications: Aug 2025
- Jasper Formal Fundamentals v2403
- Jasper Formal Fundamentas v25.03
- SystemVerilog Assertions and Formal Verification Domain
- SystemVerilog Assertions v5.1
Accomplishments
- Award issued to female students partaking a STEM course
Women in Technology (WIT) Intel Scholarship: Nov 2017 - 2020
Timeline
Logic IP Design Engineer
Intel R&D
08.2020 - 09.2025
Silicon Development DFX Intern
Intel R&D
03.2019 - 08.2019
BACHELOR OF ENGINEERING-BE - ELECTRONIC ENGINEERING
Limerick Institute of Technology
09.2016 - 05.2020
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