Integrated circuit design project (In Integrated course, 2025.03~2025.06), Sized NMOS/PMOS transistors based on VTC analysis to match rise/fall times., Designed multi-stage inverter and NAND chains for minimum delay driving external capacitive loads (20-200 fF)., Evaluated transient response and delay trade-offs through transistor-level simulation., Bearing Fault Diagnosis System project (In CICS,204.07~2025.09), Developed signal processing pipeline: low-bit quantization (down to 2-bit) → STFT → CNN classification., Achieved 99% accuracy using 2-bit quantized signals on bearing fault detection., Implemented 1st-order incremental delta-sigma ADC (OSR = 1, ENOB = 1-bit) and achieved 99% accuracy., Validated performance using both CWRU open dataset and self-measured bearing vibration data.