GIRISH WAGHMARE
Cork,Ireland
Summary
Highly skilled professional with expertise in simulation tools such as Cadence Spectre, Spectre-RF, and Keysight ADS, complemented by proficiency in design entry using Cadence Schematic Composer. Demonstrates advanced capabilities in full chip simulation with Cadence APS, Mentor AFS, and AMS simulators, as well as IC layout design using Cadence Virtuoso Layout Editor and Layout-GXL. Experienced in physical verification processes utilising Mentor Calibre DRC/LVS and Cadence DRC/LVS/PVS tools. Committed to leveraging technical expertise to contribute to innovative integrated circuit design and verification projects.
Overview
21
21
years of professional experience
2013
2013
years of post-secondary education
Work history
Senior Design Engineer – II (Analog Design)
Microchip Technology
Cork
03.2021 - 12.2025
- Working as part of Analog design team, developing new ethernet product line (10BASE-T1S Single Pair) LAN8670 PHY IC on 0.11 µm high voltage CMOS on SOI technology for Automotive Networking applications.
- Involved in Concept to volume production IC product cycle for two ethernet IC.
- Designed and verified analog blocks - Linear Voltage Regulator, Temperature Monitor, VCC Voltage monitor and RC Delay Lines.
- Translated complex system requirements into detailed block-level specifications.
- Conducted comprehensive design, schematic simulation, post-layout simulation, and verification activities.
- Performed block-level silicon characterization/post silicon validation in the lab.
- Provided critical documentation support for Production Test Team and post-silicon validation team.
- Analyzed characterization data with production testing team.
- Design porting and verification of RC relaxation oscillator and Top level verification of wakeup detector block & Contributed to Analog and Mixed Signal and top-level verifications.
- Performed jitter and timing measurements of Receiver and Transmitter blocks in Lab.
- Participated in root cause analysis of functional issues to improve product yield and reliability.
Senior Design Engineer – II (Analog Design)
Microchip Technology
Cork
03.2021 - 12.2025
- Working as part of Analog design team, developing new ethernet product line (10BASE-T1S Single Pair) LAN8670 PHY IC on 0.11 μm high voltage CMOS on SOI technology for Automotive Networking applications.
- Involved in Concept to volume production IC product cycle for two ethernet IC.
- Designed and verified analog blocks - Linear Voltage Regulator, Temperature Monitor, VCC Voltage monitor and RC Delay Lines.
- Translated complex system requirements into detailed block-level specifications.
- Conducted comprehensive design, schematic simulation, post-layout simulation, and verification activities.
- Performed block-level silicon characterization/post silicon validation in the lab.
- Provided critical documentation support for Production Test Team and post-silicon validation team.
- Analyzed characterization data with production testing team.
- Design porting and verification of RC relaxation oscillator and Top level verification of wakeup detector block & Contributed to Analog and Mixed Signal and top-level verifications.
- Performed jitter and timing measurements of Receiver and Transmitter blocks in Lab.
- Participated in root cause analysis of functional issues to improve product yield and reliability.
- Analog Design Engineer
- Dialog Semiconductor, Cork, Ireland
- January 2016 - February 2021
- Contributed to the architecture design study and circuit design of a 50-ohm output buffer stage of LNA of wideband RFIC Transceiver in 0.13μm SOI technology.
Senior Design Engineer – II (Analog Design)
Microchip Technology
Cork
03.2021 - 12.2025
- Working as part of Analog design team, developing new ethernet product line (10BASE-T1S Single Pair) LAN8670 PHY IC on 0.11 µm high voltage CMOS on SOI technology for Automotive Networking applications.
- Involved in Concept to volume production IC product cycle for two ethernet IC.
- Designed and verified analog blocks - Linear Voltage Regulator, Temperature Monitor, VCC Voltage monitor and RC Delay Lines.
- Translated complex system requirements into detailed block-level specifications.
- Conducted comprehensive design, schematic simulation, post-layout simulation, and verification activities.
- Performed block-level silicon characterization/post silicon validation in the lab.
- Provided critical documentation support for Production Test Team and post-silicon validation team.
- Analyzed characterization data with production testing team.
- Design porting and verification of RC relaxation oscillator and Top level verification of wakeup detector block & Contributed to Analog and Mixed Signal and top-level verifications.
- Performed jitter and timing measurements of Receiver and Transmitter blocks in Lab.
- Participated in root cause analysis of functional issues to improve product yield and reliability.
Analog Design Engineer
Dialog Semiconductor
01.2016 - 02.2021
- Contributed to the architecture design study and circuit design of a 50-ohm output buffer stage of LNA of wideband RFIC Transceiver in 0.13µm SOI technology.
Analog Design Engineer
Dialog Semiconductor
Cork
01.2016 - 02.2021
- Contributed to the architecture design study and circuit design of a 50-ohm output buffer stage of LNA of wideband RFIC Transceiver in 0.13µm SOI technology.
Research Assistant
Tyndall National Institute
Cork
07.2014 - 01.2016
- Contributed to the architecture study and custom design, layout, and post-layout verification of a 12-bit SAR Logic for a SAR ADC in an ultra-low power analog front-end channel for bio-medical applications (0.35 μm CMOS technology).
- Performed transistor characterization, p-cell design, and test structure design for an Analog Front end design for a SPAD Sensor in 0.35 μm CMOS Technology.
- Senior Design Engineer
- SiCon Design Technologies Pvt. Ltd, Bangalore, India
- January 2014 – June 2014
- Contributed to the architecture study, design, and post-layout verification of a 2.5GHz LC-VCO for a 2.5 GHz charge-pump based PLL in 40nm CMOS technology.
Research Assistant
Tyndall National Institute
Cork
07.2014 - 01.2016
- Contributed to the architecture study and custom design, layout, and post-layout verification of a 12-bit SAR Logic for a SAR ADC in an ultra-low power analog front-end channel for bio-medical applications (0.35 µm CMOS technology).
- Performed transistor characterization, p-cell design, and test structure design for an Analog Front end design for a SPAD Sensor in 0.35 µm CMOS Technology.
Research Assistant
Tyndall National Institute
Cork
07.2014 - 01.2016
- Contributed to the architecture study and custom design, layout, and post-layout verification of a 12-bit SAR Logic for a SAR ADC in an ultra-low power analog front-end channel for bio-medical applications (0.35 µm CMOS technology).
- Performed transistor characterization, p-cell design, and test structure design for an Analog Front end design for a SPAD Sensor in 0.35 µm CMOS Technology.
Senior Design Engineer
SiCon Design Technologies Pvt. Ltd
Bangalore
01.2014 - 06.2014
- Contributed to the architecture study, design, and post-layout verification of a 2.5GHz LC-VCO for a 2.5 GHz charge-pump based PLL in 40nm CMOS technology.
Senior Design Engineer
SiCon Design Technologies Pvt. Ltd
Bangalore
01.2014 - 06.2014
- Contributed to the architecture study, design, and post-layout verification of a 2.5GHz LC-VCO for a 2.5 GHz charge-pump based PLL in 40nm CMOS technology.
Design Engineer
Anilaneer Design Technologies Pvt. Ltd
Hyderabad
04.2011 - 12.2013
- Executed architecture study, circuit design, and post-layout verification of a 600 MHz LVDS Transmitter.
- Executed architecture study, circuit design, and post-layout verification of a curvature compensated voltage reference.
- Studied radiation hardened by design techniques, including modeling in Cadence and report preparation.
- Performed post-layout simulation and verification of the analog front-end channel (BDI pixel + column driver, video driver) for a 320 X 256 MWIR cooled infra-red Image sensor ROIC on 0.25 μm CMOS technology, including AC noise of CDS circuit and linearity simulation of video and column drivers.
- R & D Engineer
- Synopsys India Pvt. Ltd, Noida, India
- July 2010 – March 2011
- Performed verification simulations and bit-cell characterization for a 128KB Single Port Register File SRAM Memory on n55nm CMOS technology.
Design Engineer
Anilaneer Design Technologies Pvt. Ltd
Hyderabad
04.2011 - 12.2013
- Executed architecture study, circuit design, and post-layout verification of a 600 MHz LVDS Transmitter.
- Executed architecture study, circuit design, and post-layout verification of a curvature compensated voltage reference.
- Studied radiation hardened by design techniques, including modeling in Cadence and report preparation.
- Performed post-layout simulation and verification of the analog front-end channel (BDI pixel + column driver, video driver) for a 320 X 256 MWIR cooled infra-red Image sensor ROIC on 0.25 µm CMOS technology, including AC noise of CDS circuit and linearity simulation of video and column drivers.
Design Engineer
Anilaneer Design Technologies Pvt. Ltd
Hyderabad
04.2011 - 12.2013
- Executed architecture study, circuit design, and post-layout verification of a 600 MHz LVDS Transmitter.
- Executed architecture study, circuit design, and post-layout verification of a curvature compensated voltage reference.
- Studied radiation hardened by design techniques, including modeling in Cadence and report preparation.
- Performed post-layout simulation and verification of the analog front-end channel (BDI pixel + column driver, video driver) for a 320 X 256 MWIR cooled infra-red Image sensor ROIC on 0.25 µm CMOS technology, including AC noise of CDS circuit and linearity simulation of video and column drivers.
R & D Engineer
Synopsys India Pvt. Ltd
Noida
07.2010 - 03.2011
- Performed verification simulations and bit-cell characterization for a 128KB Single Port Register File SRAM Memory on n55nm CMOS technology.
R & D Engineer
Synopsys India Pvt. Ltd
Noida
07.2010 - 03.2011
- Performed verification simulations and bit-cell characterization for a 128KB Single Port Register File SRAM Memory on n55nm CMOS technology.
Design Engineer
RFIC Solutions Inc.
Nagpur
06.2007 - 07.2010
- Executed circuit design and post-layout verification of a Wide Band 1.7 to 2.7 GHz LNA in 0.25 μm SiGe technology.
- Executed circuit design and post-layout verification of a Narrow Band 2.1 to 2.5 GHz LNA in 0.5 μm GaAs technology.
- Designed and performed post-layout verification of a Bandgap Reference and LDO Voltage Regulator for a High-speed MIP Transceiver in 0.18μm CMOS technology.
- Developed the initial custom base design of a Dual modulus frequency divider for a PLL.
- Lecturer
- Institute of Petrochemical Engineering, Maharashtra, India
- June 2005 – May 2006
- Taught laboratory sessions and courses on Basic Electronics, Analog, and Digital Communication.
Design Engineer
RFIC Solutions Inc
Nagpur
06.2007 - 07.2010
- Executed circuit design and post-layout verification of a Wide Band 1.7 to 2.7 GHz LNA in 0.25 µm SiGe technology.
Design Engineer
RFIC Solutions Inc
Nagpur
06.2007 - 07.2010
- Executed circuit design and post-layout verification of a Wide Band 1.7 to 2.7 GHz LNA in 0.25 µm SiGe technology.
Lecturer
Institute of Petrochemical Engineering
, India
06.2005 - 05.2006
- Taught laboratory sessions and courses on Basic Electronics, Analog, and Digital Communication.
Lecturer
Institute of Petrochemical Engineering
, India
06.2005 - 05.2006
- Taught laboratory sessions and courses on Basic Electronics, Analog, and Digital Communication.
Education
Master of Science (MS) - Microelectronics
Manipal University
Manipal, KarnatakaBachelor of Technology(B.Tech) - Electronics and Telecommunication
Dr. Babasaheb Ambedkar Technological University
Skills
- Simulation: Cadence- Spectre, Spectre-RF, Keysight-ADS
- Design Entry: Cadence-Schematic Composer
- Full Chip Simulator: Cadence -APS, Mentor -AFS, AMS Simulator
- IC Layout: Cadence - Virtuoso Layout Editor, Layout-GXL
- Physical Verification: Mentor-Calibre DRC, LVS, & Cadence -DRC, LVS, Pvs
References
References available upon request.
Timeline
Senior Design Engineer – II (Analog Design)
Microchip Technology
03.2021 - 12.2025
Senior Design Engineer – II (Analog Design)
Microchip Technology
03.2021 - 12.2025
Senior Design Engineer – II (Analog Design)
Microchip Technology
03.2021 - 12.2025
Analog Design Engineer
Dialog Semiconductor
01.2016 - 02.2021
Analog Design Engineer
Dialog Semiconductor
01.2016 - 02.2021
Research Assistant
Tyndall National Institute
07.2014 - 01.2016
Research Assistant
Tyndall National Institute
07.2014 - 01.2016
Research Assistant
Tyndall National Institute
07.2014 - 01.2016
Senior Design Engineer
SiCon Design Technologies Pvt. Ltd
01.2014 - 06.2014
Senior Design Engineer
SiCon Design Technologies Pvt. Ltd
01.2014 - 06.2014
Design Engineer
Anilaneer Design Technologies Pvt. Ltd
04.2011 - 12.2013
Design Engineer
Anilaneer Design Technologies Pvt. Ltd
04.2011 - 12.2013
Design Engineer
Anilaneer Design Technologies Pvt. Ltd
04.2011 - 12.2013
R & D Engineer
Synopsys India Pvt. Ltd
07.2010 - 03.2011
R & D Engineer
Synopsys India Pvt. Ltd
07.2010 - 03.2011
Design Engineer
RFIC Solutions Inc.
06.2007 - 07.2010
Design Engineer
RFIC Solutions Inc
06.2007 - 07.2010
Design Engineer
RFIC Solutions Inc
06.2007 - 07.2010
Lecturer
Institute of Petrochemical Engineering
06.2005 - 05.2006
Lecturer
Institute of Petrochemical Engineering
06.2005 - 05.2006
Bachelor of Technology(B.Tech) - Electronics and Telecommunication
Dr. Babasaheb Ambedkar Technological University
Master of Science (MS) - Microelectronics
Manipal University